Lecture, four hours; outside study, eight hours. Requisites: courses M51A, 180. Detailed study of various problems in logic-level synthesis of VLSI digital systems, including two-level Boolean network optimization; multilevel Boolean network optimization; technology mapping for standard cell designs and field-programmable gate-array (FPGA) designs; retiming for sequential circuits; and applications of binary decision diagrams (BDDS). Letter grading.